1. Field of the Invention
The present invention relates to a clock control circuit and a semiconductor device including the clock control circuit, and more particularly relates to a clock control circuit that adjusts a phase or a duty cycle of a clock signal, such as a DLL circuit and a duty-cycle compensation circuit, and a semiconductor device that includes the clock control circuit.
2. Description of Related Art
In recent years, a synchronous memory that performs an operation in synchronization with a clock signal has been widely used as a main memory for a personal computer and the like. In particular, in a synchronous memory device of a DDR (Double Data Rate) type among various types of synchronous memory devices, a DLL circuit that generates an internal clock signal synchronized with an external clock signal is an essential component because it is necessary to synchronize input/output data with the external clock signal in a precise manner (see Japanese Patent Application Laid-open No. 2008-217947).
Such a DLL circuit includes a counter circuit that updates its count value based on a phase of the external clock signal and a delay line that generates the internal clock signal by delaying the external clock signal based on the count value of the counter circuit. The update of the count value is performed in a predetermined sampling period. For this reason, when a result of determining the phase is temporarily reversed due to a noise and the like at a timing at which the count value is updated, the count value is updated in a direction opposite to its intended direction. That is, a delay amount of the delay line that should be increased may be decreased, or conversely, a delay amount that should be decreased may be increased.
In some cases, a jitter component is superimposed on the external clock signal. The jitter component is a fluctuation in a clock frequency, and this fluctuation has a predetermined frequency. When the jitter component affects the DLL circuit, in some cases, a loop that repeats an up count and a down count in an alternate manner is formed despite the phase is considerably out of synchronization, from which it cannot escape.
Meanwhile, a period for locking the DLL circuit is defined by the standards. Therefore, if the delay line is adjusted to the opposite direction due to a noise or if the loop is formed due to a jitter component, the DLL circuit cannot be locked within the period defined by the standards.
In this way, in the conventional DLL circuit, there has been a problem that it cannot be properly locked when affected by a noise or a jitter component. This kind of problem also occurs in other types of clock control circuits that control a clock signal, not only the DLL circuit, such as a duty-cycle compensation circuit for compensating a duty cycle of an internal clock signal. That is, even in the duty-cycle compensation circuit, if it is affected by a noise or a jitter component, its internal clock signal may not be adjusted to a desired duty cycle.